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CXA2581N
RF Signal Processor for CD Players
Description The CXA2581N is an RF signal processing IC for compact disc players. Features * Wide band RF signal processing * RF system VCA circuit * RF system equalizer (supports CAV mode) * Supports pickups with built-in RF summing amplifier * Low current consumption mode (EQ Pass mode) * RW/ROM switching mode * Center error amplifier * Output DC level shift circuit * TE balance adjustment function Functions * RF AC summing amplifier, equalizer, VCA * RF DC summing amplifier * Focus error amplifier * Tracking error amplifier * Center error amplifier * Automatic power control * VC buffer amplifier (analog block, digital block) Pin Configuration
DC_OFST RFDCO RFDCI TE_BAL
30 pin SSOP (Plastic)
Absolute Maximum Ratings * Supply voltage VCC 7 * Storage temperature Tstg -65 to +150 * Allowable power dissipation PD 620
V C mW
Operating Conditions * Operating supply voltage range VCC - GND 3.4 to 5.5 V (0V Vcc - DVcc < 2V) Note) Care should be taken for the operating voltage. See page 18. * Operating temperature Topr -30 to +85 C
RFC
VFC
BST
RFG
VCC
CEI
VC
FEI 17 14 DVC
CE
TE
30
29
28
27
26
25
24
23
22
21
20
19
18
16
1 LD
2 PD
3 EQ_IN
4 AC_SUM
5 GND
6 A
7 B
8 C
9 D
10 E
11 F
12 SW
13 DVCC
15 RFAC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
FE
E98739A97-PS
CXA2581N
Block Diagram
AC_SUM
EQ_IN
RFG
RFC EQ
4 AC SUM
3
23 AC VCA
24 26 25
VFC
BST
15 RFAC EQ_ON/OFF
RW/ROM
30 DC_OFST 29 RFDCI 28 RFDCO DVC
DVCC VC A B C D 6 7 8 9 VOFST RW/ROM VC RW/ROM VC F 10 gm VOFST DVCC DVC DVCC RW/ROM
17 FEI 16 FE
19 TE_BAL
RW/ROM
18 TE E 11 gm VOFST B C A D DVC DVCC 21 CEI 20 CE VC RW/ROM APC-OFF (Hi-Z) DVC RW/ROM VC (H/L) VCC VC VCC DVC VC RW/ROM
SW 12 PD LD 2 1 APC
VOFST VC DVC 13 DVCC
22 VCC
5 GND
27 VC
14 DVC
-2-
CXA2581N
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol LD PD EQ_IN AC_SUM GND A B C D E F SW DVCC DVC RFAC FE FEI TE TE_BAL CE CEI VCC RFG BST VFC RFC VC RFDCO RFDCI DC_OFST I/O O I I O I I I I I I I I I O O O I O I O I I I I I I O O I I APC amplifier output. APC amplifier input. RFAC system VCA block and EQ block input. RFAC system RF SUM output. GND. A signal input. B signal input. C signal input. D signal input. E signal input. F signal input. Mode switching signal input. DVCC. DVC output. RFAC signal output. Focus error signal output. FE amplifier virtual ground. Tracking error signal output. TE balance adjustment. Center error signal output. CE amplifier virtual ground. VCC. RFAC system VCA block low frequency gain adjustment. EQ boost level adjustment. EQ cut-off frequency adjustment. EQ cut-off frequency adjustment. VC voltage output. RFDC signal output. RFDC amplifier virtual ground. RFDC signal output offset adjustment. Description
-3-
CXA2581N
Pin Description Pin No. Symbol I/O Equivalent circuit Description
10k
1
LD
O
1 1k
APC amplifier output.
55k
2
PD
I
2
20k
APC amplifier input.
20k
1.1k
1.1k
3
EQ_IN
I
3 5k VC
1.2k 5k VC
Equalizer circuit input.
1.6k 1.6k
4
AC_SUM
O
4
RFAC summing amplifier output.
5
GND
--
--
GND.
-4-
CXA2581N
Pin No.
Symbol
I/O
Equivalent circuit
Description
6
A
I
15k 6 100A
7
B
I
7 100A 30k
RF summing amplifier and focus error amplifier input.
47k
8
C
I
8 100A 47k 9 VC 100A
9
D
I
10
E
I
10 11 VC
Tracking error amplifier input.
11
F
I
200k
12
SW
I
200k 12 200k VC
CD-ROM/RW switching input. RW when connected to VCC, ROM when connected to GND.
13
DVCC
--
--
Digital power supply.
14
DVC
O
150k 14 150k 25
(DVCC + GND)/2 voltage output.
-5-
CXA2581N
Pin No.
Symbol
I/O
Equivalent circuit
Description
15
RFAC
O
2mA 100
15
RFAC amplifier output.
16
FE
O
50k VC 124 16
Focus error amplifier output.
124 17
17
FEI
I
Focus error amplifier gain adjustment. The gain is adjusted by the external resistance value connected between this pin and Pin 16.
18
TE
O
18 20k
Tracking error amplifier output.
19 20k
19
TE_BAL
I
20k
Tracking error E and F gain balance adjustment.
VC
20
CE
O
50k VC 124 20
Center error amplifier output.
124 21
21
CEI
I
Center error amplifier gain adjustment. The gain is adjusted by the external resistance value connected between this pin and Pin 20.
-6-
CXA2581N
Pin No. 22
Symbol VCC
I/O --
Equivalent circuit --
Description VCC. (AVCC)
20k
23
RFG
I
23 VC 100A
Sets the RFAC low frequency gain.
50A
24
BST
I
20k 24 VC
Input for adjusting the equalizer circuit boost level.
20k
25
VFC
I
25 VC 100A
Input for adjusting the equalizer circuit boost frequency with the control voltage.
1.0V 124
26
RFC
I
26
Input for adjusting the equalizer circuit boost frequency with external resistance.
27
VC
O
150k 27 150k 25
(VCC + GND)/2 voltage output.
-7-
CXA2581N
Pin No.
Symbol
I/O
Equivalent circuit
Description
28
RFDC
O
1mA 2k VC 124 124 28
RFDC amplifier output.
29
RFDCI
I
29
RFDC amplifier gain adjustment. The gain is adjusted by the external resistance value connected between this pin and Pin 28.
30
124
30
DC_OFST
I
24k VC 10k 15k
RFDC amplifier offset control.
-8-
CXA2581N
Description of Functions * RFAC The RF signal input by connecting capacitance to the EQ_IN pin is equalized, arithmetically amplified and then output from the RFAC pin.
A B C D AC_SUM 6 7 8 9 4 AC SUM BST VFC 24 25 26 RFC VCC
5.1k
0.1
RF EQ_IN
3 RFG 23 RW/ROM
EQ
Amp
15 RFAC
BST = VCC
Low frequency gain AC_SUM: 13dB (both ROM/RW) VCA to RFAC ROM: 0dB RW: 12dB
The EQ can be bypassed by connecting the BST control pin (Pin 24) to VCC. In this case only the EQ block enters sleep mode and low power consumption mode (slim mode) is activated. The low frequency gain is the same value as for EQ ON mode. If RF (summing signal) is present at the pickup output pin, input the addition output signal to EQ_IN (Pin 3) coupled by capacitance. When using a pickup without a summing output function, perform addition with the AC SUM block and then input the signal to EQ_IN (Pin 3) coupled by capacitance. RW/ROM switching is done by the VCA block, so either input method can be used without problem. The RW gain is 12dB higher than the ROM gain.
Gain [dB]
VCA variable range
The VCA low frequency gain can be adjusted by the RFG (Pin 23) voltage. The control voltage vs. low frequency gain characteristics are shown in the graph to the right.
8 0 -8 Vcnt [V]
VC - 1
VC
VC + 1
The RFAC pin (Pin 15) is an NPN transistor emitter follower output. The maximum drive current is approximately 2mA. If the load capacitance distorts the output waveform, connect resistance between Pin 15 and GND to increase the drive current. -9-
CXA2581N
* EQ The diagram to the left shows the EQ internal block diagram. The EQ consists of a combination of HPF and LPF. The HPF and LPF transmittance is the Bessel function. The boost gain can be adjusted by adjusting the HPF gain. The boost frequency is adjusted by the RFC external resistance value and the VFC control voltage value. RFC resistance value: The cut-off frequency fo of each filter is adjusted by the Pin 26 external resistance value. The VFC voltage can be varied using this fo as the reference. VFC voltage: fo can be changed by the voltage applied to Pin 25.
In
HPF
Amp
LPF fc Boost
LPF
Out
EQ CNT RFC 26 VFC 25 BST 24
VCC
VC
VC
The boost gain can be adjusted by the BST pin control voltage. The control characteristics are shown in the graph below.
Boost Gain [dB]
The cut-off frequency control characteristics are shown in the graph below.
fc [Hz]
8dB
1.5fo
fo
0dB Vcnt [V]
0.5fo Vcnt [V]
VC - 1.0
VC VC + 1.0 Pin 24 (BST) voltage
VC - 1.0
VC VC + 1.0 Pin 25 (VFC) voltage
* APC (Automatic Power Control) When the laser diode is driven by a constant current, the optical power output has extremely large negative temperature characteristics. Therefore, the current must be controlled to maintain the monitor photo diode output at a constant level. This control is performed by the APC function.
VCC 56k PD 2 10k 55k 10k 10k 1.25V 56k 1 LD 1k
- 10 -
CXA2581N
* Focus Error The signals input to the A and C pins and the B and D pins are arithmetically amplified and the focus error signal is output. This circuit has RW/ROM switching and offset addition functions.
VC ROM 23.5k A6 C8 B7 D9 ROM VOFST RW FE = Gain { (B + D) - (A + C) } Low frequency gain ROM: 16dB RW: 28dB Cut-off frequency fc (typ.) ROM: 300kHz RW: 300kHz 30k 30k 30k ROM 30k 47k 200k 47k 200k RW DVC RW FEI 17 100k 124 50k 124 16 FE 100k
* Tracking Error The signals input to the E and F pins are arithmetically amplified and the tracking error signal is output. This circuit has RW/ROM switching and offset addition functions.
TE_BAL 19 TE = Gain (F - E) ROM VOFST 20k 10 20k 11 F VC gm RW 20k 20k VC 31.5k ROM 251k 10k 251k RW DVCC 18 TE gm 10k 125.5k RW DVC 63k 63k ROM Low frequency gain ROM: 16dB RW: 28dB
TE balance adjustment F - E low frequency gain = 6dB
E
External resistance value vs. Low frequency gain
Low frequency gain [dB] 22 16 12.5
10k
20k
30k
Resistance value []
- 11 -
CXA2581N
* VC Buffer This outputs the VC ((1/2) VCC) voltage. The maximum output current is approximately 3mA. Use this voltage as the analog block VC voltage.
* DVC Buffer This outputs the 1/2 DVCC voltage. The maximum output current is approximately 3mA. Use this voltage as the digital block VC voltage. The output DC voltage of each block is level shifted using the DVC voltage as the reference.
DVCC 40k
VCC
VC 27 25 40k DVC 14 25
40k
40k
* RFDC The signals input to the A, B, C and D pins are added, amplified and the RFDC signal is output. RW/ROM switching and low frequency gain adjustment are possible.
VC 30 ROM 24k A6 B7 C8 D9 ROM VC RW 15k 15k 15k 15k 2.4k 3.3k DVC 40k RW 96k 10k ROM RW 124 2k 124 RFDCI 29 5.1k 28 RFDCO
RFDC = Gain (A + B + C + D) Low frequency gain ROM: 17.5dB RW: 29.5dB fc (Typ) ROM: 20MHz RW: 5MHz The gain can be adjusted by the external resistance connected between Pins 28 and 29. The output voltage offset can be adjusted by controlling the Pin 30 voltage.
- 12 -
CXA2581N
* Center Error The signals input to the A and D pins and the B and C pins are arithmetically amplified and the center error signal is output. RW/ROM switching, low frequency gain adjustment and offset adjustment are possible.
VC ROM 12k A6 D9 B7 C8 ROM VOFST RW 30k 30k 30k ROM 30k 24k 96k 24k 96k RW DVC RW 48k CEI 21 50k 200k 20 CE
The (B + C) - (A + D) signal is arithmetically amplified. Low frequency gain ROM: 16dB RW: 28dB
Cut-off frequency fc (typ.) ROM: 200kHz RW: 200kHz
* Output Offset Shift The RFDC, FE, TE and CE output DC voltages are level shifted to the digital VC voltage (DVC). The reference voltage of this IC is the VC voltage, and only the output reference voltage changes. The maximum output voltage of each output signal should be kept to the digital VCC voltage (DVCC) or less in order to protect the DSP_IC.
40k 40k DVC VC 40k 40k VC VOFST
The VC and DVC voltages are arithmetically amplified and output as the VOFST voltage. The VOFST voltage serves as the level shift reference voltage, and is distributed to each block.
* SW This controls the laser (APC) on/off, active/sleep mode, and RW/ROM mode switching. Switching is controlled by the voltage applied to the SW pin.
Active/Sleep SW 12 SW RW/ROM APC_ON/OFF
SW high/low condition High: VC + 1V to Vcc Low: VC - 1V to GND
The VC buffer is always in active mode even if it enters sleep mode. In the function block, MODE_SW is always set to active mode.
Control voltage
Item VCC
APC ON OFF ON
Active/Sleep Active Sleep Active
RW/ROM RW -- ROM - 13 -
VC or Hi-Z GND
Electrical Characteristics
Switch conditions V1 V1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 amplitude frequency E1 E2 E4 0V 1.7V 0V Hi-Z 22 4 OOOO 0.1Vp-p 100kHz 70mV 4 4 4 4 15 15 1.4Vp-p 100kHz -1.0V 0V 1.0V -1.0V 0V 1.0V 0V 1.7V 10MHz 0.3Vp-p 0.3Vp-p 30MHz 20MHz 1.2V -1.2V 0V -1.0V 1.0V 1.7V 0V 0V 0.8Vp-p 100kHz 0.3Vp-p 100kHz O 0.35Vp-p 50kHz 0.2Vp-p 50kHz O O 15 15 15 15 15 15 15 15 15 15 15 15 0.1Vp-p 0.4V -0.4V 0V O O O O O O O O O O O OO OO 10MHz 70mV OOOO OOOO OOOO Pin voltage 20 log (Vout/Vin) Pin current 13 Pin current 22 Pin current 15 0.2 3 0V 0V 0V 30 22 Pin current 50 30 E5 E6 0V 0V E3 0V MeasureE7 ment pin Measurement conditions Bias conditions Min. Typ. Max. Unit 70 mA 45 mA 0.5 0.8 mA 5 8 mA -1.2 -0.7 -0.2 V 11 13 15 dB 20 log (Vout/Vin) - Gsum -2.5 -0.5 0.5 dB Pin voltage -ACSUM_Ofst 1.4 1.6 1.7 V Pin voltage -ACSUM_Ofst -0.5 -0.3 -0.1 V Pin voltage Pin voltage -0.8 -0.3 0.2 -0.8 -0.3 0.2 20 log (Vout/Vin) - Gac_ROM2 -11 20 log (Vout/Vin) 20 log (Vout/Vin) - Gac_ROM2 -3 5 20 log (Vout/Vin) - Gac_RW2- Gac_ROM2 -11 20 log (Vout/Vin) - Gac_ROM2 9 20 log (Vout/Vin) - Gac_RW2- Gac_ROM2 5 20 log (Vout/Vin) 20 log (Vout/Vin) - Gac_ROM2 0.3Vp-p 20 log (Vout/Vin) - Gac_ROM2 20 log (Vout/Vin) - EQoff -2 2 2 -8 0 8 -8 12 8 0 5 5 V V -5 dB 3 dB 11 dB -5 dB 15 dB 11 dB 2 8 8 dB dB dB -0.5 2.5 5.5 dB Pin voltage - AC_OfstROM 0.8 1 1.2 V
(VCC = 1.7V, VEE = -1.7V, DVCC = 1.7V, DVEE = -1.7V)
Measure- Funcment No. tion
Measurement item
Symbol
1
Current consumption (Active, EQ On) Icc_Aeqon
2
Current consumption (Active, EQ Off) Icc_Aeqoff
3
Current consumption (DVCC)
Icc_Dvcc
4
Current consumption (Sleep)
Icc_Slp
5
SUM offset voltage
ACSUM_Ofst
6
SUM low frequency gain
Gsum
RFAC SUM
7
SUM frequency response
Fsum
8
SUM maximum output voltage H Vsum_H
9
SUM maximum output voltage L Vsum_L
10
Offset voltage ROM
AC_OfstROM
RFAC EQ
- 14 -
75mVp-p 50kHz 0.8Vp-p 100kHz
11
Offset voltage RW
AC_OfstRW
12
Low frequency gain ROM_min
Gac_ROM1
13
Low frequency gain ROM_cnt
Gac_ROM2
14
Low frequency gain ROM_max Gac_ROM3
15
Low frequency gain RW_min
Gac_RW1
16
Low frequency gain RW_cnt
Gac_RW2
17
Low frequency gain RW_max Gac_RW3
18
Low frequency gain EQ_off
Gac_EQoff
19
Frequency response Min_L
Fac_MinL
20
Frequency response Min_H Fac_MinH
21
Frequency response EQ_OFF Fac_EQoff
22
Maximum output voltage H
Vac_H
CXA2581N
23
Maximum output voltage L
Vac_L
Pin voltage - AC_OfstROM -1.1 -0.9 -0.7 V
Switch conditions V1 V1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 amplitude frequency E1 E2 E4 0V 0V Pin voltage Pin voltage 20 log (Vout/Vin) 20 log (Vout/Vin) - Gdc_ROM -150 0 -150 0 28 50mVp-p 100kHz 28 28 28 28 0.3V -0.3V 0V 0V O O O O O O O O O O O O O O O O O O O O O 0.1Vp-p 300kHz 25mVp-p 300kHz 25mVp-p 300kHz 0.3V 0.3V 0.1Vp-p 300kHz O O 25mVp-p 1kHz O 1kHz 25mVp-p O 0.1Vp-p 1kHz 1kHz 0.1Vp-p -0.5V 28 28 16 16 16 16 16 16 16 16 16 16 16 16 28 O 50mVp-p 20MHz O 12.5mVp-p 5MHz 12.5mVp-p 100kHz 28 0V 0V E5 E6 0V 0V E3 0V O OOOO OOOO OOOO OOOO OOOO OOOO MeasureE7 ment pin Min. Typ. Max. Unit 150 mV 150 mV Measurement conditions
Bias conditions
Measure- Funcment No. tion
Measurement item
Symbol
24
Offset voltage ROM
DC_OfstROM
25
Offset voltage RW
DC_OfstRW
26
Low frequency gain ROM
Gdc_ROM
14.5 17.5 20.5 dB 10 12 14 dB
27
Low frequency gain RW
Gdc_RW
29
RFDC
28
Frequency response ROM
Fdc_ROM
20 log (Vout/Vin) - Gdc_ROM -3.5 -0.5 0.5 dB 20 log (Vout/Vin) - Gdc_RW - Gdc_ROM -4.5 -1.5 -0.5 dB Pin voltage Pin voltage Pin voltage Pin voltage Pin voltage 20 log (Vout/Vin) 20 log (Vout/Vin) 20 log (Vout/Vin) - Gfe_ROM1 20 log (Vout/Vin) - Gfe_ROM2 0.6 0.8 1 V -1.7 -1.5 -1.3 V -0.7 -0.6 -0.5 V -150 -150 0 0 150 mV 150 mV 12.5 15.5 18.5 dB 12.5 15.5 18.5 dB 10 10 12 12 14 dB 14 dB 20 log (Vout/Vin) - Gfe_ROM1 -5.5 -2.5 0.5 dB 20 log (Vout/Vin) - Gfe_ROM2 -5.5 -2.5 0.5 dB 20 log (Vout/Vin) - Gfe_RW1- Gfe_ROM1 -5.5 -2.5 0.5 dB 20 log (Vout/Vin) - Gfe_RW2- Gfe_ROM2 -5.5 -2.5 0.5 dB Pin voltage Pin voltage 1.3 1.5 1.7 V -1.7 -1.5 -1.3 V
Frequency response RW
Fdc_RW
30
Maximum output voltage H
Vdc_H
31
Maximum output voltage L
Vdc_L
32
Offset voltage 1
DC_Ofst1
33
Offset voltage ROM
FE_OfstROM
34
Offset voltage RW
FE_OfstRW
39
FE
- 15 -
35
Low frequency gain ROM1
Gfe_ROM1
36
Low frequency gain ROM2
Gfe_ROM2
37
Low frequency gain RW1
Gfe_RW1
38
Low frequency gain RW2
Gfe_RW2
Frequency response ROM1 Ffe_ROM1
40
Frequency response ROM2 Ffe_ROM2
41
Frequency response RW1
Ffe_RW1
42
Frequency response RW2
Ffe_RW2
43
Maximum output voltage H
Vfe_H
44
Maximum output voltage L
Vfe_L
CXA2581N
Switch conditions MeasureMin. Typ. Max. Unit -200 0 0 16 13 10 10 16 12 12 -500 13 200 mV 500 mV 19 dB 19 dB 14 dB 14 dB E4 0V 18 0.1Vp-p 18 18 18 18 18 18 18 18 1.0V -1.0V 0.6V 0.6V 0V O O OO 0.1Vp-p O OO O OO O OO OO O O O O O O O O 25mVp-p 25mVp-p O 1kHz 1kHz 1kHz 0.1Vp-p 200kHz 0.1Vp-p 200kHz 25mVp-p 200kHz 25mVp-p 200kHz 0.5V 0.5V O 0.1Vp-p 1kHz 0V 18 18 18 18 20 20 20 20 20 20 20 20 20 20 20 20 20 log (Vout/Vin) 20 log (Vout/Vin) - Gte_ROM1 20 log (Vout/Vin) - Gte_ROM2 O 0.1Vp-p O 25mVp-p 25mVp-p 0.1Vp-p 100kHz O 0.1Vp-p 100kHz O 25mVp-p 100kHz 25mVp-p 100kHz 0.1Vp-p 0.1Vp-p 1kHz 1kHz OO OO OO O O O 1kHz 1kHz OO O 1kHz O 1kHz 20 log (Vout/Vin) Pin voltage 0V 0V 0V 18 Pin voltage E5 E6 E7 ment pin V1 V1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 amplitude frequency E1 E2 0V 0V E3 0V O O Measurement conditions
Bias conditions
Measure- Funcment No. tion
Measurement item
Symbol
45
Offset voltage ROM
TE_OfstROM
46
Offset voltage RW
TE_OfstRW
47
Low frequency gain ROM1
Gte_ROM1
48
Low frequency gain ROM2
Gte_ROM2
49
Low frequency gain RW1
Gte_RW1
50
Low frequency gain RW2
Gte_RW2
52
TE
51
Frequency response ROM1 Fte_ROM1
20 log (Vout/Vin) - Gte_ROM1 -3.2 -1.2 0.8 dB 20 log (Vout/Vin) - Gte_ROM2 -3.2 -1.2 0.8 dB 20 log (Vout/Vin) - Gte_RW1- Gte_ROM1 -3.5 -1.5 0.5 dB 20 log (Vout/Vin) - Gte_RW2- Gte_ROM2 -3.5 -1.5 0.5 dB E, F gain difference E, F gain difference Pin voltage Pin voltage Pin voltage Pin voltage 20 log (Vout/Vin) 20 log (Vout/Vin) 4 -8 1.3 6 -6 8 dB -4 dB 1.5 1.7 V -1.7 -1.5 -1.3 V -150 -150 0 0 150 mV 150 mV 12.5 15.5 18.5 dB 12.5 15.5 18.5 dB 20 log (Vout/Vin) - Gce_ROM1 10 20 log (Vout/Vin) - Gce_ROM2 10 12 12 14 dB 14 dB 20 log (Vout/Vin) - Gce_ROM1 -3.8 -2.3 -0.8 dB 20 log (Vout/Vin) - Gce_ROM2 -3.8 -2.3 -0.8 dB 20 log (Vout/Vin) - Gce_RW1- Gce_ROM1 -3.8 -2.3 -0.8 dB 20 log (Vout/Vin) - Gce_RW2- Gce_ROM2 -3.8 -2.3 -0.8 dB Pin voltage Pin voltage 1.15 1.35 1.55 V -1.7 -1.5 -1.3 V
Frequency response ROM2 Fte_ROM2
53
Frequency response RW1
Fte_RW1
54
Frequency response RW2
Fte_RW2
55
Balance gain 1
Gte1
56
Balance gain 2
Gte2
65
CE
- 16 -
57
Maximum output voltage H
Vte_H
58
Maximum output voltage L
Vte_L
59
Offset voltage ROM
CE_OfstROM
60
Offset voltage RW
CE_OfstRW
61
Low frequency gain ROM1
Gce_ROM1
62
Low frequency gain ROM2
Gce_ROM2
63
Low frequency gain RW1
Gce_RW1
64
Low frequency gain RW2
Gce_RW2
Frequency response ROM1 Fce_ROM1
66
Frequency response ROM2 Fce_ROM2
67
Frequency response RW1
Fce_RW1
68
Frequency response RW2
Fce_RW2
69
Maximum output voltage H
Vce_H
CXA2581N
70
Maximum output voltage L
Vce_L
Switch conditions V1 V1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 amplitude frequency E1 E2 E4 0V
Input at which output voltage = 0V
Bias conditions E3 E5 0V 0 0.5 0.75 1 1 1 1 O 27 14 Pin voltage Pin voltage Pin voltage Pin voltage Pin voltage Pin voltage 0V 0V 1, 2 E6 0V MeasureE7 ment pin Min. Typ. Max. Unit 150 300 mV 1 V Measurement conditions
Measure- Funcment No. tion
Measurement item O 0V 0V O O O Hi-Z 0V
Symbol
71
Output voltage 1
Vapc1
72
Output voltage 2
Vapc2
APC
73
Output voltage 3
Vapc3
Vapc1 + 20mV Vapc1 - 20mV
-1 -0.75 -0.5 V 1.4 1.6 1.7 V -0.55 -0.15 0.25 V -100 0 -100 0 100 mV 100 mV
74
APC OFF voltage
Vapc_off
75
Maximum output current
Iapc_max O O
76
Output voltage
Vavc
DVC AVC
77
Output voltage
Vdvc
- 17 -
CXA2581N
CXA2581N
Notes on Supply Voltage
6.5
6 Vcc (Pin 22) [V]
5.5
5
4.5
4
2
2.5 DVcc (Pin 13) [V]
3
3.5
VCC voltage value at which the waveform is clipped when DVCC is fixed
The voltage difference between VCC (Pin 22) and DVCC (Pin 13) should be kept to the value shown in the graph above or less. Example) When DVCC = 2.5V From the graph, VCC = 4.5V Therefore, VCC should be from 3.4 to 4.5V. (3.4V is the minimum operating voltage for the IC.) Electrical Characteristics Measurement Circuit
VCC 5.1k E6 30 DC_OFST 29 RFDCI 28 RFDCO 10k S12 27 VC VCC 200k E5 25 VFC 24 BST E4 23 RFG E3 22 VCC 21 CEI 20 CE 19 TE_BAL 10k E7 18 TE 10k 100k 17 FEI 16 FE 15 10k DVCC RFAC 10k
5.1k 26 RFC
AC_SUM
EQ_IN
DVCC 13
GND
1 S1 S2
2 S3
3
4
5 10k VEE S5
6
7
8
9 20k
10
11 20k
12
14
S4 0.8mA E2
S6
S7
S8
S9
S10
S11
0.1 VEE VCC VCC VEE V1 E1
- 18 -
DVC
SW
PD
LD
C
D
A
B
E
F
CXA2581N
Application Circuits
30 DC_OFST 29 RFDCI
RFDC OUT VC 0.1
VCC
CE OUT
TE OUT
FE OUT
28 RFDCO
27 VC
26 RFC
25 VFC
24 BST
23 RFG
22 VCC
21 CEI
20 CE
19 TE_BAL
18 TE
17 FEI 14 DVC
16 FE 15 RFAC
AC_SUM
EQ_IN
1
2
3
4
5
6
7
8
9
10
11
12
13
0.1 LD PD IN A B C D E Drive RF SUM RF SUM inputs the signal when A, B, C and D are added by the front and PD.
F
DVCC DVC MODE RFAC Control OUT
<CXA2581N> VCC VCC 0.1 EQ_IN 0.1 RFG BST RFC VFC

AC_SUM 4 AC SUM 3
23 AC VCA
24 26 25
EQ 15 EQ_ON/OFF
DVCC
GND
SW
PD
LD
C
D
A
B
E
F
RFAC
RFAC
A VC B VC C VC D VC
A B C D
RF VC RW/ROM
30 29 28 DVC
DC_OFST RFDCI RFDC
DVCC VC A B C D A B C D 6 7 8 9 VOFST VC
RW/ROM VOFST
RW/ROM
RFDCO FEI
DVCC DVC
17 16
FE
FE
19 TE_BAL
F VC
F
F 10 E 11 gm
VC
RW/ROM
DVCC 18 TE TE
E E VC
gm VOFST B C A D DVC DVCC 21 20 VC RW/ROM APC-OFF (Hi-Z) DVC RW/ROM VC (H/L) VCC VC DVC
VC
RW/ROM CEI CE
CE
SW 12 PD LD VC GND VCC 22 VCC 2 1 APC
VOFST VC DVC 13 DVCC VCC
VC 5 GND 27 VC DVC 14
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 19 -
CXA2581N
Characteristics Graphs
EQ Rfc resistance value vs. Frequency response
8 Vbst = VC, Vfc = VC 7 Rfc = 20k Rfc = 5.1k 6 5 4 [dB] [dB] 3 2 1 0 -1 -2 0.1 1 [MHz] 10 100 Rfc = 100k 8 6 4 2 0 -2 -4 -6 -8 0.1 1 [MHz] 10 100
Rfc = 100k Vboost = -1.0V Rfc = 5.1k Vboost = -1.0V Rfc = 100k Vboost = 0V Rfc = 5.1k Vboost = 0V
EQ boost voltage vs. Frequency response
12 Vfc = VC 10
Rfc = 100k Vboost = 1.0V Rfc = 5.1k Vboost = 1.0V
EQ Vfc vs. frequency response
8 Vbst = VC 7 6 5 4 [dB] 3 2 1 0 -1 -2 0.1 1 [MHz] 10 100 [dB] Rfc = 20k Vfc = -1V Rfc = 20k Vfc = 0V Rfc = 20k Vfc = 1V 24 21 18 15 12 9 6 3 0 -3 -6 0.1 AC SUM
RF AC frequency response
EQ_Pass RW mode
EQ_Pass ROM mode
1 [MHz]
10
100
RF DC frequency response
38 35 32 RW 29 26 [dB] [dB] 23 20 17 14 11 8 0.1 1 [MHz] 10 100 ROM 25 22 19 16 13 10 7 4 0.01 ROM 34 31 28 RW
FE frequency response
0.1 [MHz]
1
10
- 20 -
CXA2581N
TE frequency response
35 32 29 26 23 [dB] 20 17 16 13 1.5 10 1.0 7 0.01 0.1 [MHz] 1 10 0.5 0.05 ROM RW VLD - Output voltage [V] 5.5 5.0 4.5
APC I/O characteristics
Vcc = 5.5V 4.0 3.5 3.0 2.5 Vcc = 3.4V 2.0
0.1
0.15 VPD - Input voltage [V]
0.2
0.25
CE frequency response
34 31 28 25 22 [dB] 19 16 13 10 7 4 0.01 0.1 [MHz] 1 10 ROM RW
- 21 -
CXA2581N
Package Outline
Unit: mm
30PIN SSOP (PLASTIC)
+ 0.2 1.25 - 0.1 9.7 0.1
0.10
30
16
5.6 0.1
A
1 + 0.1 0.22 - 0.05 0.13 M
15 0.65 + 0.05 0.15 - 0.02
0.1 0.1
0 to 10 NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-30P-L01 SSOP030-P-0056 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.1g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
- 22 -
0.5 0.2
7.6 0.2

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